A processor will flush each level of cache memory before entering a low-power mode (e.g., a sleep mode). This flush prevents losing recently modified data during the low-power mode. To perform this flush, each level of cache memory is walked and modified data is written back to main memory. The time and power associated with performing this flush are overhead that limits the power savings provided by entering the low-power mode for brief periods of time. Accordingly, there is a need for techniques that reduce the number of modified cache lines in a level of cache memory.